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2.6.11
ATM/UTOPIA/POS Timing
Table 47 provides the ATM/UTOPIA/POS input and output AC timing specifications.
Table 47. ATM/UTOPIA/POS AC Timing (External Clock) Specifications
Characteristic
Outputs—External clock delay
Symbol
t UEKHOV
Min
1
Max
9
Unit
ns
Outputs—External clock High
Impedance 1
t UEKHOX
1
9
ns
Inputs—External clock input setup time
Inputs—External clock input hold time
Notes:
1.
Not tested. Guaranteed by design.
t UEIVKH
t UEIXKH
4
1
ns
ns
2.
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams
also apply when the falling edge is the active edge.
Figure 32 provides the AC test load for the ATM/UTOPIA/POS.
Output
Z 0 = 50 Ω
R L = 50 Ω
V DD /2
Figure 32. ATM/UTOPIA/POS AC Test Load
Figure 33 shows the ATM/UTOPIA/UTOPIA timing with external clock.
CLK (input)
t UEIVKH
t UEIXKH
Input Signals:
t UEKHOV
Output Signals:
t UEKHOX
Figure 33. ATM/UTOPIAPOS AC Timing (External Clock)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
60
Freescale Semiconductor
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